Interconnect structure fabricated without dry plasma etch processing

ABSTRACT

An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/483,588, filed Jun. 12, 2009 the entire content and disclosure ofwhich is incorporated herein by reference.

BACKGROUND

The invention relates generally to interconnect structures withinmicroelectronic structures. More particularly, the invention relates tomethods for efficiently fabricating interconnect structures withinmicroelectronic structures.

Microelectronic structures, such as but not limited to semiconductorstructures, are typically fabricated using microelectronic substrateswithin, upon and/or over which are located and formed microelectronicdevices. The microelectronic devices are connected and interconnectedusing patterned conductor layers that are separated by dielectriclayers. Such sub-structures that comprise such patterned conductorlayers that are separated by dielectric layers within microelectronicstructures are conventionally understood within the microelectronicfabrication art as interconnect structures.

As microelectronic fabrication technology has advanced, the complexityof interconnect structures has also increased. Thus, interconnectstructures within microelectronic structures typically comprise severalinterconnecting patterned conductor layers that are separated bydielectric layers that are interposed between the severalinterconnecting patterned conductor layers. In order to provide foroptimal performance of interconnect structures, patterned conductorlayers within interconnect structures typically comprise coppercontaining conductor materials that provide for enhanced microelectroniccircuit speed, while dielectric layers within interconnect structurestypically comprise comparatively low dielectric constant dielectricmaterials (i.e., having a dielectric constant from 1.0 to 4.3) thatprovide for reduced cross-talk between adjacent patterned conductorlayers within an interconnect structure.

While copper containing conductor materials and comparatively lowdielectric constant dielectric materials are thus desirable within themicroelectronic fabrication art for fabricating interconnect structureswith enhanced performance, copper containing conductor materials and lowdielectric constant dielectric materials are nonetheless not entirelywithout problems in the microelectronic fabrication art for fabricatinginterconnect structures with enhanced performance. In that regard, adensity of patterned conductor layers within an interconnect structuremay provide for reflective based processing difficulties within aninterconnect structure when fabricating an overlying patterned conductorlayer within the interconnect structure. In addition, low dielectricconstant dielectric materials are also often difficult to effectivelyand reproducibly pattern absent damage while using conventional dryplasma etch methods.

Thus, desirable are interconnect structures within microelectronicstructures and methods for fabricating interconnect structures withinmicroelectronic structures that provide for readily fabricatedinterconnect structures with enhanced interconnect structureperformance.

BRIEF SUMMARY

In one embodiment of the invention, an interconnect structure within amicroelectronic structure and a method for efficiently fabricating theinterconnect structure within the microelectronic structure areprovided.

The interconnect structure in accordance with an embodiment of theinvention first includes a substrate that further includes a firstconductor layer located embedded within a base dielectric layer locatedover the substrate, and optionally also includes a first self-alignedcapping layer located aligned upon the first conductor layer. Theinterconnect structure also includes, sequentially layered upon theforegoing intermediate structure: (1) a patterned bottom anti-reflectivecoating layer located upon the foregoing intermediate structure; and (2)at least one patterned inter-level dielectric layer located upon thepatterned bottom anti-reflective coating layer. The patterned bottomanti-reflective coating layer and the at least one patterned inter-leveldielectric layer define an aperture over the first conductor layer. Eachof the patterned bottom anti-reflective coating layer and the patternedinter-level dielectric layer has a particular material composition.

The particular method for fabricating the interconnect structurementioned above sequentially forms: (1) the first self-aligned cappinglayer self-aligned to the first conductor layer formed over thesubstrate; (2) a developable but not imageable bottom anti-reflectivecoating layer that may be developed to form the patterned bottomanti-reflective coating layer; and (3) at least one imageableinter-level dielectric layer that may be imaged and developed to formthe patterned inter-level dielectric layer. The imageable inter-leveldielectric layer is sequentially imaged and developed, and thedevelopable bottom anti-reflective coating layer is sequentiallydeveloped, to form the patterned bottom anti-reflective coating layerand the patterned inter-level dielectric layer that provide the apertureover the first conductor layer.

No dry plasma etch processing is used for forming the first self-alignedcapping layer, the patterned bottom anti-reflective coating layer or theat least one patterned inter-level dielectric layer. Thus, theinterconnect structure may be fabricated efficiently absent dry plasmaetch processing damage to the patterned inter-level dielectric layer,that may comprise a comparatively low dielectric constant dielectricmaterial (i.e., having a dielectric constant from 1.0 to 4.3, measuredin vacuum).

A particular microelectronic structure that includes an interconnectstructure in accordance with an embodiment of the invention includes:(1) a first conductor layer located within a base dielectric layerlocated over a substrate; (2) a patterned bottom antireflective coatinglayer located upon the base dielectric layer; and (3) at least onepatterned inter-level dielectric layer located upon the patterned bottomanti-reflective coating layer. The patterned bottom anti-reflectivecoating layer and the at least one patterned inter-level dielectriclayer define an aperture located over the first conductor layer. Thepatterned bottom anti-reflective coating layer includes an elementselected from the group consisting of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni,Hf and La. The at least one patterned inter-level dielectric layercomprises a cured organic functionalized silicon containing dielectricmaterial.

Another particular microelectronic structure that includes aninterconnect structure in accordance with an embodiment of the inventionincludes: (1) a first conductor layer located within a base dielectriclayer located over a substrate; (2) a first conductor capping layerlocated aligned upon the first conductor layer; (3) a patterned bottomanti-reflective coating layer located upon the base dielectric layer;and (4) at least one patterned inter-level dielectric layer located uponthe patterned bottom anti-reflective coating layer. The patterned bottomanti-reflective coating layer and the at least one patterned inter-leveldielectric layer define an aperture that exposes the first conductorcapping layer. The developed bottom anti-reflective coating layerincludes an element selected from the group consisting of C, Si, Ge, B,Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one patterned inter-leveldielectric layer comprises an organic functionalized silicon containingdielectric material.

A particular method for fabricating a microelectronic structure thatincludes an interconnect structure in accordance with an embodiment ofthe invention includes forming over a substrate that includes a firstconductor layer formed within a base dielectric layer a developable butnot imageable bottom anti-reflective coating layer. This particularmethod also includes forming upon the developable but not imageableanti-reflective coating layer at least one imageable inter-leveldielectric layer. This particular method also includes imaging anddeveloping the imageable inter-level dielectric layer and developing thedevelopable but not imageable bottom anti-reflective coating layer toform a patterned inter-level dielectric layer formed upon a patternedbottom anti-reflective coating layer that defines an aperture locatedover the first conductor layer.

Another particular method for fabricating a microelectronic structurethat includes an interconnect structure in accordance with an embodimentof the invention includes forming self-aligned upon a first conductorlayer formed within a base dielectric layer formed over a substrate afirst capping layer. This particular method also includes forming overthe substrate that includes the first capping layer formed upon thefirst conductor layer formed within the base dielectric layer adevelopable but not imageable bottom anti-reflective coating layer. Thisparticular method also includes forming upon the developable but notimageable bottom anti-reflective coating layer at least one imageableinter-level dielectric layer. This particular method also includesimaging and developing the at least one imageable inter-level dielectriclayer and developing the developable but not imageable bottomanti-reflective coating layer to form a patterned inter-level dielectriclayer formed upon a patterned bottom anti-reflective coating layer thatdefines an aperture located over the first conductor layer.

BRIEF DESCRIPTION THE DRAWINGS

FIG. 1 to FIG. 7 show a series of schematic cross-sectional diagramsillustrating the results of progressive stages in fabricating amicroelectronic structure that includes an interconnect structure inaccordance with a particular embodiment of the invention.

FIG. 1 shows the microelectronic structure at an early stage in thefabrication therein of the interconnect structure.

FIG. 2 shows a first self-aligned capping layer located and formed upona first conductor layer within the interconnect structure within themicroelectronic structure of FIG. 1.

FIG. 3 shows a developable bottom anti-reflective coating layer locatedand formed upon the microelectronic structure of FIG. 2, and animageable inter-level dielectric layer located and formed upon thedevelopable bottom anti-reflective coating layer.

FIG. 4 shows the results of imaging and developing the imageableinter-level dielectric layer and developing the developable bottomanti-reflective coating layer within the microelectronic structure ofFIG. 3 to provide a damascene aperture that is bounded by a patternedbottom anti-reflective coating layer and a patterned inter-leveldielectric layer.

FIG. 5 shows a second imageable inter-level dielectric layer located andformed upon the microelectronic structure of FIG. 4.

FIG. 6 shows the results of imaging and developing the second imageableinter-level dielectric layer within the microelectronic structure ofFIG. 5 to provide a dual damascene aperture that is bounded by thepatterned anti-reflective coating layer, the patterned first inter-leveldielectric layer and a patterned second inter-level dielectric layer.

FIG. 7 shows a second conductor layer comprising a contiguouos via andinterconnect located and formed into the dual damascene aperture that isillustrated within the microelectronic structure of FIG. 6.

DETAILED DESCRIPTION

The invention, which comprises an interconnect structure that may bereadily fabricated within a microelectronic structure absent dry plasmaetch processing, and a method for readily fabricating the interconnectstructure within the microelectronic structure absent the dry plasmaetch processing, is understood within the context of the Description ofthe Preferred Embodiment, as set forth below. The Description of thePreferred Embodiment is understood within the context of the drawingthat are described above. Since the drawings are intended forillustrative purposes, the drawings are not necessarily drawn to scale.

FIG. 1 to FIG. 7 show a series of schematic cross-sectional diagramsillustrating the results of progressive stages in fabricating aninterconnect structure within a microelectronic structure in accordancewith a particular embodiment of the invention.

FIG. 1 shows a substrate 10. A base dielectric layer 12 is located andformed upon the substrate 10. A first barrier layer 14 is located andformed embedded within the base dielectric layer 12 and a firstconductor layer 16 is also located and formed embedded within the basedielectric layer 12 and separated from the base dielectric layer 12 bythe barrier layer 14.

Each of the foregoing substrate 10 and overlying layers 12/14/16 maycomprise materials and have dimensions that are otherwise generallyconventional in the microelectronic fabrication art, and in particularthe semiconductor fabrication art. Each of the foregoing substrate 10and overlying layers 12/14/16 may also be formed using methods that areotherwise generally conventional in the microelectronic fabrication art,and in particular the semiconductor fabrication art.

The substrate 10 may comprise any type of substrate that may be used asa base substrate in fabricating a microelectronic structure. Thus,particular substrates that may be used for the substrate 10 includedielectric substrates (i.e., such as but not limited to ceramicsubstrates and glass-ceramic substrates) and semiconductor substrates.When the substrate 10 comprises a semiconductor substrate, such asemiconductor substrate may comprise any of several semiconductormaterials. Non-limiting examples of semiconductor materials includesilicon, germanium, silicon-germanium alloy, silicon-carbon alloy,silicon-germanium-carbon alloy and compound (i.e., III-V and II-VI)semiconductor materials. Non-limiting examples of compound semiconductormaterials include gallium arsenide, indium arsenide and indium phosphidesemiconductor materials. Typically, the substrate 10 comprises a siliconor silicon-germanium alloy semiconductor material that has a thicknessfrom 0.1 to 1 millimeters.

Although FIG. 1 implicitly illustrates this particular embodiment withinthe context of a bulk semiconductor substrate comprising the substrate10, this particular embodiment is not intended to be so limited. Rather,this instant particular embodiment and alternative embodiments may alsobe practiced under certain circumstances using asemiconductor-on-insulator substrate (that would otherwise result fromthe presence of a buried dielectric layer interposed within a thicknessof a bulk semiconductor substrate). Alternatively, this particularembodiment also contemplates use of a hybrid orientation (HOT) substratefor the substrate 10 when the substrate 10 comprises a semiconductorsubstrate. A hybrid orientation substrate includes multiplecrystallographic orientation semiconductor regions supported by a singlesemiconductor substrate.

Although not particularly illustrated within the schematiccross-sectional diagram of FIG. 1, when the substrate 10 comprises asemiconductor substrate, the semiconductor substrate will typicallyinclude located and formed therein and/or thereupon microelectronicdevices, such as but not limited to semiconductor devices. Suchmicroelectronic devise may include, but are not necessarily limited to,resistors, transistors, diodes and capacitors that may be connected andinterconnected using an interconnect structure in accordance with theembodiment and the invention.

The base dielectric layer 12 comprises a dielectric material. Suitabledielectric materials include, but are not necessarily limited to,comparatively higher dielectric constant dielectric materials (i.e.,having a dielectric constant greater than 4.3 to 20, measured invacuum), such as but not limited to silicon oxide dielectric materials,silicon nitride dielectric materials and silicon oxynitride dielectricmaterials (i.e., although oxides, nitrides and oxynitrides of otherelements are not excluded). Also included, but also not limiting, aregenerally lower dielectric constant dielectric materials (i.e., having adielectric constant from 1.0 to less than 4.3, measured in vacuum), suchas but not limited to spin-on-glass dielectric materials,spin-on-polymer dielectric materials, micro-porous dielectric materials,nano-porous dielectric materials, carbon doped silicate glass dielectricmaterials and fluorine doped silicate glass dielectric materials.

Either one of the foregoing generally higher dielectric constantdielectric materials and generally lower dielectric constant dielectricmaterials may be fabricated using methods and materials that areotherwise generally conventional in the microelectronic fabrication art.Included in particular, but also not limiting, are spin-on methods,chemical vapor deposition methods and physical vapor deposition methods.Typically, the base dielectric layer 12 comprises at least in-part asilicon oxide material, that may comprise a generally lower dielectricconstant dielectric material, that has a thickness from 50 to 2000nanometers.

The first barrier layer 14 comprises a barrier material. Suitablebarrier materials include, but are not necessarily limited to conductorbarrier materials and dielectric barrier materials. Conductor barriermaterials are generally more common, although dielectric barriermaterials are also known.

Conductor barrier materials that may be used for forming the barrierlayer 14 include, but are not necessarily limited to titanium, tantalum,ruthenium and tungsten conductor barrier materials, alloys of titanium,tantalum, ruthenium and tungsten conductor barrier materials andnitrides of titanium, tantalum, ruthenium and tungsten conductor barriermaterials, as well as laminates and composites of any of the foregoingconductor barrier materials. Any of the foregoing conductor barriermaterials may be formed using methods that are otherwise generallyconventional in the microelectronic fabrication art. Such methods mayinclude, but are not necessarily limited to, thermal or plasmanitridation methods, chemical vapor deposition methods (i.e., includingbut not limited to atomic layer deposition methods) and physical vapordeposition methods. Typically, the barrier layer 14 comprises a titaniumor tantalum conductor barrier material or a nitride of a titanium,tantalum or tungsten conductor barrier material, that has a conformalthickness (i.e., a single thickness) from 1 to 100 nanometers locatedand formed embedded within the base dielectric layer 12.

The conductor layer 16 comprises a conductor material. Aluminum, copperand tungsten containing conductor materials are common conductormaterials within the microelectronic fabrication art, and moreparticularly within the semiconductor fabrication art. Also included,but also not limiting, are alloys of the foregoing conductor materials.The foregoing conductor materials may in general be formed using methodsand materials analogous, equivalent or identical to the methods andmaterials that are used for forming the barrier layer 14 when comprisedof a conductor barrier material. Also included are plating methods forforming the conductor layer 16. Typically, the conductor layer 16comprises a copper or copper containing conductor material that has athickness from 25 to 1000 nanometers located and formed upon the barrierlayer 14 as embedded within the base dielectric layer 12.

Although not a limitation of this particular embodiment of theinvention, the microelectronic structure of FIG. 1 may in a firstinstance be fabricated by forming a precursor layer to the basedielectric layer 12 upon the substrate 10. Such a precursor layer to thebase dielectric layer 12 may then be etched to provide an aperture intowhich is located and formed a blanket first barrier layer precursor tothe first barrier layer 14 and a blanket first conductor layer precursorto the first conductor layer 16. Such a blanket first barrier layerprecursor may be formed using a method such as but not limited to achemical vapor deposition method or a physical vapor deposition method.Such a blanket first conductor layer precursor may be formed using aplating method. The blanket first conductor layer precursor and theblanket first barrier layer precursor may then be sequentiallyplanarized to provide the first conductor layer 16 located and formednested within the first barrier layer 14 located and formed within theaperture. Such planarizing may be effected using planarizing methodsthat are otherwise generally conventional in the microelectronicfabrication art. Mechanical planarizing methods and chemical mechanicalpolish planarizing methods are common.

FIG. 2 shows a self-aligned capping layer 18 located and formed alignedupon (i.e., aerially co-extensive with in plan-view) and capping thefirst conductor layer 16 within the microelectronic structure of FIG. 1.

Within this particular embodiment, the self-aligned capping layer 18comprises a conductor capping material that can be located and formed byselective deposition upon a copper conductor material or a coppercontaining conductor material from which the first conductor layer 16 ispreferably comprised, and not on the dielectric material from which thebase dielectric layer 12 is comprised. Particular conductor cappingmaterials that are contemplated within the instant embodiment that maybe selectively deposited to form the self-aligned capping layer 18include, but are not necessarily limited to, stoichiometric andnon-stoichiometric alloys of CoWP, CoWB, CuSiN, NiMoP, CoWMoB and CoWPB.Such conductor capping materials may be formed selectively self-alignedwith respect to the first conductor layer 16 while using methodsincluding but not limited to plating methods. Typically, theself-aligned capping layer 18 is located and formed upon the firstconductor layer 16 to a thickness from 1 to 10 nanometers.

Although the left hand side of FIG. 2 illustrates the embodiment withinthe context of a self-aligned capping layer 18 that is located andformed upon the first conductor layer 16 that is planarized with respectto the base dielectric layer 12, alternatively, the embodiment alsocontemplates that the first conductor layer 16 may be embedded withinand recessed within the base dielectric layer 12, and thus theself-aligned capping layer 18 located and formed planarized with respectto the base dielectric layer 12. Such an alternative of this firstembodiment is illustrated within the right hand side of FIG. 2, whichincludes the first conductor layer 16′ that is embedded within andrecessed within the base dielectric layer 12. Under such circumstances,the embodiment also contemplates that the self-aligned capping layer 18may be formed of a non-selectively blanket deposited conductor cappingmaterial or dielectric capping material that is subsequently planarizedto provide the embedded and recessed self-aligned capping layer 18. Suchnon-selectively deposited conductor capping materials may include, butare not necessarily limited to conductor materials that are analogous,equivalent or identical to the conductor barrier materials from whichmay be comprised the first barrier layer 14. Such non-selectivelydeposited dielectric barrier materials may include, but are notnecessarily limited to, dielectric materials that are analogous,equivalent or identical to the dielectric materials from which may becomprised the base dielectric layer 12.

FIG. 3 shows a developable bottom anti-reflective coating layer 20located and formed upon the microelectronic structure of FIG. 2. FIG. 3also shows a first imageable inter-level dielectric layer 22 located andformed upon the developable bottom anti-reflective coating layer 20.

Similarly with other bottom anti-reflective coating materials that aregenerally known in the microelectronic fabrication art, a developablebottom anti-reflective coating material in accordance with thisparticular embodiment comprises an organic liquid coating material thatis typically intended to be used in conjunction with an overlyingphotoresist material layer during a photolithographic process stepincident to fabrication of a microelectronic structure. Distinguishingthe developable bottom anti reflective coating layer 20 in accordancewith the instant embodiment from an otherwise generally conventionalbottom anti-reflective coating layer is the characteristic that thedevelopable bottom anti-reflective coating layer 20 may be developedsequentially with development of a resist layer that is located andformed upon the developable bottom anti-reflective coating layer 20.Thus, the developable bottom anti-reflective coating layer 20 inaccordance with this particular embodiment serves as a generallyconventional bottom anti-reflective coating layer. As will beillustrated within the context of further discussion below, a developeddevelopable bottom anti-reflective coating layer 20 in accordance withthe embodiment will remain in place as a patterned bottomanti-reflective coating and thus also serve in-part as a portion of aninter-level dielectric layer incident to further processing of themicroelectronic structure whose schematic cross-sectional diagram isillustrated in FIG. 3. Typically, the developable bottom anti-reflectivecoating layer 20 has a thickness from 5 to 200 nanometers, and thedevelopable bottom anti-reflective coating layer 20 is not intended tohave imageable properties, although under certain circumstances thedevelopable anti-reflective coating material may have imageableproperties.

The imageable inter-level dielectric layer 22 comprises an imageableinter-level dielectric material. Within the context of furtherdiscussion below, the imageable inter-level dielectric layer 22typically comprises a functionalized polymer having one or moreacid-sensitive functional groups that impart imageability to theimageable inter-level dielectric layer 22. Within the context of theinstant embodiment, such a functionalized polymer may be imaged anddeveloped (i.e., patterned) using photolithographic methods, anddesirably may be converted into a low dielectric constant patternedinter-level dielectric layer polymer after subsequent processing, thatmay include, but is not necessarily limited to, thermal processing orradiation processing.

Within the context of the instant embodiment, the developable bottomanti-reflective coating layer 20 is typically, but not necessarily,formed by a liquid deposition process including but not limited tospin-on coating, spray coating, dip coating, brush coating, evaporationor chemical solution deposition. A particular developable bottomanti-reflective coating layer 20 that is formed by the liquid depositionmethod comprises a polymer that includes at least one monomer unitcomprising the formula M-R1 wherein M is at least one of C, Si, Ge, B,Sn, Fe, Ta, Ti, Ni, Hf and La and R1 is a chromophore. Alternatively, Mmay include at least one of Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, eitherwith or without Si and also independently with or without C.

In some particular embodiments, M within the monomer unit may also bebonded to an organic ligand including atoms of C and H, a cross-linkingcomponent or another chromophore, or combinations thereof. The organicligand may further include at least one of O, N, S and F. When theorganic ligand is bonded to M, the organic ligand is bonded to M throughC, O, N, S.

In other particular embodiments, the developable bottom anti-reflectivecoating layer 20 formed by liquid deposition may also include at leastone second monomer unit, in addition to the at least one monomer unitrepresented by the formula M-R1. When present, at least one secondmonomer unit has the formula M′-R2, wherein M′ is at least one of C, Si,Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La, and R2 is a cross-linking agent.Alternatively, M′ may include at least one of Ge, B, Sn, Fe, Ta, Ti, Ni,Hf and La, either with or without Si, and also independently with orwithout C. M and M′ may be the same or different elements. In these twoformulae, M and M′ within the two separate monomer units may also bebonded to organic ligands including atoms of C and H, a cross-linkingcomponent, a chromophore or mixtures thereof. The organic ligands mayfurther include one of O, N, S and F. When the organic ligand is bondedto M and M′, it is bonded to M or M′ through C, O, N, S.

The liquid developable bottom anti-reflective coating layer 20compositions comprising M-R1, or M-R1 and M′—R2 may also comprise atleast one additional component, including but not limited to a separatecross-linking monomer, an acid generator and/or a solvent.

In this particular embodiment, the developable bottom anti-reflectivecoating 20 formed by liquid deposition is desirably characterized by thepresence of a stoichiometric or non-stoichiometric silicon oxide (i.e.,SiO) containing polymer having pendant chromophore moieties. The siliconoxide containing polymer may be a polymer containing SiO moieties in thepolymer backbone and/or in pendant groups. Preferably, the polymercontains SiO moieties in the polymer backbone. The polymer is preferablya siloxane, a silane, a carbosilane, an oxycarbosilane, anorganosilicate, a silsesquioxane, or an organosiloxane, more preferablyorganosilsesquioxane. The polymer should have solution and film-formingcharacteristics conducive to forming the developable bottomanti-reflective coating layer 20 by conventional spin-coating. Inaddition to the chromophore moieties discussed above, the SiO-containingpolymer also preferably contains a plurality of reactive sitesdistributed along the SiO containing polymer for reaction with across-linking component.

The first imageable inter-level dielectric layer 22 typically comprisesan imageable dielectric material that has a comparatively low dielectricconstant (i.e., from 1.0 to less than 4.3) either as initially depositedor as subsequently processed. Such an imageable dielectric material isalso formed using a generally conventional deposition process includingbut not limited to spin-on-coating, spray coating, dip coating, brushcoating, and evaporation. Subsequent to forming the first imageableinter-level dielectric layer 20, a post deposition baking step isoptionally, but nonetheless typically, required to remove unwantedcomponents, such as solvent based components. When performed, the bakingstep is conducted at a temperature from 60° to 200° C., with a bakingtemperature from 80° to 140° C. being even more preferred. The durationof such a baking process step varies, depending upon particularmaterials compositions, solvents and baking temperatures.

A thickness of the first imageable inter-level dielectric layer 22 mayvary depending on the technique used to form the first imageableinter-level dielectric layer 22, as well as the material of compositionof the first imageable inter-level dielectric layer 22. Typically, thefirst imageable inter-level dielectric layer 22 has a thickness from 10to 10000 nanometers, with a thickness from 50 to 2000 nanometers beingmore typical.

As suggested above, the first imageable inter-level dielectric layer 22first functions as a photoresist layer and may then optionally, ifappropriate, be converted into a comparatively low dielectric constantmaterial layer incident to post patterning processing. Examples of postprocessing include, but are not necessarily limited to, thermaltreatment, ultraviolet light treatment, electron beam treatment, ionbeam treatment, microwave treatment, plasma treatment, or combinationsof the foregoing treatments. As an example, the first imageableinter-level dielectric layer 22 may comprise a functionalized polymerhaving one or more acid-sensitive groups that impart imageablecharacteristics to the first imageable inter-level dielectric layer 22.These polymers or blends of polymers can be converted into acomparatively low dielectric constant dielectric material aftersubsequent processing.

More specifically, the first imageable inter-level dielectric layer 22comprises acid-sensitive (typically photo generated acid) polymers ofhydrocarbons, fluorinated hydrocarbons, siloxane, silane, carbosilane,oxycarbosilane, organosilicates, silsesquioxanes and the like. Thepolymers include, for example, silsesquioxane-type polymers includingcaged, linear, branched or combinations thereof. In a particularsub-embodiment, the first imageable inter-level dielectric layer 22comprises a blend of these acid-sensitive polymers. The first imageableinter-level dielectric 22 may further comprise at least one sacrificialpore generator to reduce the dielectric constant when forming the firstimageable inter-level dielectric 22 in a cured form. Further examples ofimageable inter-level dielectric materials that may be used for thefirst imageable inter-level dielectric layer 22 within the context ofthe instant embodiment are taught within U.S. Pat. Nos. 7,041,748,7,056,840, and 6,087,064, the teachings of all of which are incorporatedherein by reference in their entirety.

The first imageable inter-level dielectric layer 22 preferably has adielectric constant after cure, generally no greater than 4.3. Thedielectric constant may be greater than 1.0 and less than 4.3, morepreferably from 1.0 to 3.6, even more preferably from 1.0 to 3.0,further more preferably from 1.0 to 2.5, with 1.0 to 2.0 being mostpreferred.

The first imageable inter-level dielectric layer 22 is preferably formedfrom a composition that includes one of the above mentioned polymers orpolymer blends, a photoacid generator, a base additive and a solventtypically used in a photoresist type composition. The photoacidgenerators, base additives and solvents are generally conventional inthe microelectronic fabrication art and will be discussed further below.

Within this particular embodiment, the first imageable inter-leveldielectric layer 22 may comprise a negative-tone imageable inter-leveldielectric material comprising a silsesquioxane polymer or copolymerincluding, for example, but not limited to, poly(methylsilsesquioxane)(PMS), poly(p-hydroxybenzylsilsesquioxane) (PHBS),poly(p-hydroxyphenylethylsilsesquioxane) (PHPES),poly(p-hydroxyphenylethylsilsesquioxane-co-p-hydroxy-alpha-methylbenzylsilsesquioxane) (PHPE/HMBS),poly(p-hydroxyphenylethylsilsesquioxane-co-methoxybenzylsilsesquioxane)(PHPE/MBS),poly(p-hydroxyphenylethylsilsesquioxane-co-t-butylsilsesquioxane)(PHPE/BS),poly(p-hydroxyphenylethylsilsesquioxane-co-cyclohexylsilsesquioxane)(PHPE/CHS),poly(p-hydroxyphenylethylsilsesquioxane-co-phenylsilsesquioxane)(PHPE/PS),poly(p-hydroxyphenylethylsilsesquioxane-co-bicycloheptylsilsesquioxane)(PHPE/BHS), polyp-hydroxy-alpha-methylbenzylsilsesquioxane) (PHMBS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-hydroxybenzylsilsesquioxane)(PHMB/HBS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-methoxybenzylsilsesquioxane)(PHMB/MBS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-t-butylsilsesquioxane)(PHMB/BS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-cyclohexylsilsesquioxane)(PHMB/CHS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-phenylsilsesquioxane)(PHMB/PS),poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-bicycloheptylsilsesquioxane)(PHMB/BHS),poly(p-hydroxybenzylsilsesquioxane-co-p-hydroxyphenylethylsilsesquioxane)(PHB/HPES), andpoly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilsesquioxane)(PHMB/MBS).

When the first imageable inter-level dielectric layer 22 comprises ablended polymer component, the silsesquioxane polymer in the blend maybe selected from the silsesquioxane polymers described above or may beselected from other silsesquioxane polymers such as, for example, butnot limited to poly(methyl-silsesquioxane) (PMS),poly(p-hydroxybenzylsilsesquioxane) (PHBS),poly(p-hydroxybenzylsilsesquioxane-co-methoxybenzylsilsesquioxane)(PHB/MBS),polyp-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilsesquioxane)(PHMB/MBS), poly(p-hydroxybenzylsilsesquioxane-co-t-butylsilsesquioxane)(PHB/BS),poly(p-hydroxybenzylsilsesquioxane-co-cyclohexylsilsesquioxane)(PHB/CHS), poly(p-hydrooxybenzylsilsesquioxane-co-phenylsilsesquioxane)(PHB/PS),poly(p-hydroxybenzylsilsesquioxane-co-bicycloheptylsilsesquioxane)(PHB/BHS), and caged silsesquioxanes such asoctakis(glycidyloxypropyl)dimethylsilyloxy)silsesquioxane,octakis[cyclohexenyl epoxide) dimethylsilyloxy]silsesquioxane,octakis[4-(hydroxyphenylethyl) dimethylsilyloxy]silsesquioxane, andoctakis[{2-(1′,1′-bis(trifluoromethyl)-1′-hydroxyethyl)norbornyl}dimethylsilyloxy]silsesquioxane.If desired, a combination of different silsesquioxane polymers may beused in the blend with the non-silsesquioxane polymer.

Alternatively, for a positive tone first imageable inter-leveldielectric layer 22 a silicon-containing polymer employed within acoating composition may include a homopolymer or a copolymer. Suitabletypes of such silicon-containing polymers include homopolymers orcopolymers containing at least one monomer selected from the groupconsisting of a siloxane, a silane, a silsesquioxane and a silyne.Highly preferred silicon-backbone polymers are selected from the groupconsisting of poly(hydroxyphenyl alkyl)silsesquioxanes andpoly(hydroxyphenyl alkyl) siloxanes, wherein the alkyl is a C₁₋₃₀moiety. These preferred silicon-containing polymers are preferably fullyor partially protected with acid-sensitive protecting groups.

The positive-tone material for forming the first imageable inter-leveldielectric layer 22 may comprise blends of a non-silicon containingpolymer and a silicon-containing polymeric additive with asilicon-containing substituent bonded to the polymeric backbone, thesilicon-containing polymeric additive may be a homopolymer or copolymercontaining at least one monomer having a silicon-containing substituent.The silicon-containing substituent may or may not be acid sensitive.Typically, however the substituent is acid sensitive when containing aC₂ alkyl moiety. Preferably, the silicon-containing substituent isattached to a monomer selected from the group consisting ofhydroxystyrene, an acrylate, a methacrylate, an acrylamide, amethacrylamide, itaconate, an itaconic half ester or a cycloolefin.Preferred silicon-containing substituents include: siloxane, silane andcubic silsesquioxanes. The silicon-containing polymer may furtherinclude silicon-free monomers such as those selected from the groupconsisting of styrene, hydroxystyrene, acrylic acid, methacrylic acid,itaconic acid and an anhydride such as maleic anhydride and itaconicanhydride.

Preferred monomers containing silicon-containing substituents aretrimethylsilyl alkyl acrylate, trimethylsilyl alkyl methacrylate,trimethylsilyl alkyl itaconate, tris(trimethylsilyl)silyl alkyl acrylatetris(trimethylsilyl)silyl alkyl methacrylate, tris(trimethylsilyl)silylalkyl itaconate, tris(trimethylsilyloxy)silyl alkyl acrylate,tris(trimethylsilyloxy)silyl alkyl methacrylate,tris(trimethylsilyloxy)silyl alkyl itaconate, alkylsilyl styrene,trimethylsilylmethyl(dimethoxy)silyloxy alkyl acrylate,trimethylsilylmethyl(dimethoxy)silyloxy alkyl methacrylate,trimethylsilylmethyl(dimethoxy)silyloxy alkyl itaconate, trimethylsilylalkyl norbornene-5-carboxylate alkyl, tris(trimethylsilyl)silyl alkylnorbornene-5-carboxylate and tris(trimethylsilyloxy)silyl alkylnorbornene-5-carboxylate, wherein alkyl is a C₁₋₅ moiety.

Highly preferred species of these monomers are3-(3,5,7,9,11,13,15-heptacyclopentylpentacyclo[9.5.1.13,9.15,15.17,13]-octasiloxan-1-yl)propylmethacrylate,1,3,5,7,9,11,13-heptacyclopentyl-15-vinylpentacyclo[9.5.1.13,9.15,15.17,13]octasiloxane,methacrylamidotrimethylsilane,O-(methacryloxyethyl)-N-(triethoxysilylpropyl)urethane,methacryloxyethoxytrimethylsilane,N-(3-methacryloxy-2-hydroxypropyl)-3-aminopropyltriethoxysilane,(methacryloxymethyl)bis(trimethylsiloxy)methylsilane,(m,p-vinylbenzyloxy)trimethylsilane,methacryloxypropyltris(trimethylsiloxy)silane,methacryloxytrimethylsilane,3-methacryloxypropylbis(trimethylsiloxy)methylsilane,3-methacryloxypropyldimethylchlorosilane,methacryloxypropyldimethylethoxysilane,methacryloxypropyldimethylmethoxysilane,methacryloxypropylheptacyclopentyl-T8-silsequioxane,methacryloxypropylmethyldichlorosilane,methacryloxypropylmethyldiethoxysilane,methacryloxypropylmethyldimethoxysilane,(methacryloxymethyl)dimethylethoxysilane,(methacryloxymethyl)phenyldimethylsilane(phenyldimethylsilyl)methylmethacrylate,methacryloxymethyltriethoxysilane, methacryloxymethyltrimethoxysilane,methacryloxymethyltris(trimethylsiloxy)silane,O-methacryloxy(polyethyleneoxy)trimethylsilane,methacryloxypropylpentamethyldisiloxane, methacryloxypropylsilatrane,methacryloxypropylsiloxane macromer, methacryloxypropyl terminatedpolydimethylsiloxane, methacryloxypropyltrichlorosilane,methacryloxypropyltriethoxysilane, methacryloxypropyltrimethoxysilane,methacryloxypropyltris(methoxyethoxy)silane,p-(t-butyldimethylsiloxy)styrene, butenyltriethoxysilane,3-butenyltrimethylsilane, (3-acryloxypropyl)trimethoxysilane,(3-acryloxypropyl)tris(trimethylsiloxy)silane,O-(trimethylsilyl)acrylate, 2-trimethylsiloxyethlacrylate,N-(3-acryloxy-2-hydroxypropyl)-3-aminopropyltriethoxysilane,(3-acryloxypropyl)dimethylmethoxysilane,(3-acryloxypropyl)methylbis(trimethylsiloxy)silane,(3-acryloxypropyl)methyldichlorosilane, and(3-acryloxypropyl)methyldimethoxysilane,(3-acryloxypropyl)trichlorosilane.

Within the instant embodiment, the extent of protection and the amountof co-monomer present in the silicon containing polymeric additive aresuch that the first imageable inter-level dielectric layer 22 willprovide desirable lithography performance, i.e., high resolution andacceptable process window. Examples of protecting groups which may beemployed are cyclic and branched (secondary and tertiary) aliphaticcarbonyls, esters or ethers containing from 3 to 30 carbon atoms,acetals, ketals and aliphatic silylethers.

Examples of cyclic or branched aliphatic carbonyls that may be employedin the present embodiment include, but are not limited to, phenoliccarbonates; t-alkoxycarbonyloxys such as t-butoxylcarbonyloxy andisopropyloxycarbonyloxy. A highly preferred carbonate ist-butoxylcarbonyloxy.

Examples of cyclic and branched ethers that may be employed in thepresent embodiment include, but are not limited to, benzyl ether andt-alkyl ethers such t-butyl ether. Of the aforesaid ethers, it is highlypreferred to use t-butyl ether.

Examples of cyclic and branched esters that can be employed in thepresent invention include, but are not limited to carboxylic estershaving a cyclic or branched aliphatic substituent such as t-butyl ester,isobornyl ester, 2-methyl-2-admantyl ester, benzyl ester,3-oxocyclohexanyl ester, dimethylpropylmethyl ester, mevalonic lactonylester, 3-hydroxy-g-butyrolactonyl ester, 3-methyl-g-butylrolactonylester, bis(trimethylsilyl)isopropyl ester, trimethylsilylethyl ester,tris(trimethylsilyl)silylethyl ester and cumyl ester.

Examples of acetals and ketals that can be employed in the presentinvention include, but are not limited to, phenolic acetals and ketalsas well as tetrahydrofuranyl, tetrahydropyranyl, 2-ethoxyethyl,methoxycyclohexanyl, methoxycyclopentanyl, cyclohexanyloxyethyl,ethoxycyclopentanyl, ethoxycyclohexanyl, methoxycycloheptanyl andethoxycycloheptanyl. Of these, it is preferred that amethoxycyclohexanyl ketal be employed.

Illustrative examples of silylethers that can be employed in the presentinvention include, but are not limited to, trimethylsilylether,dimethylethylsilylether and dimethylpropylsilylether. Of thesesilylethers, it is preferred that trimethylsilylether be employed.

In a particular embodiment for a negative-tone first imageableinter-level dielectric layer 22 of the instant embodiment, two miscible,or compatible, silsesquioxane polymers are included. A firstsilsesquioxane polymer is a linear, branched, caged compound orcombination thereof having the following structural formula:

wherein each occurrence of R₁ is one or more acidic functional groupsfor base solubility; each occurrence of R₂ is a carbon functionality forcontrolling polymer dissolution in an aqueous base; R₁ is not equal toR₂; m and n represent the number of repeating units; m is an integer;and n is zero or an integer greater than zero. In the presentembodiment, R₁ is not limited to any specific functional group, and ispreferably selected from among linear or branched alkyls which aresubstituted with OH, C(O)OH, and/or F; cycloalkyls which are substitutedwith OH, C(O)OH, and/or F; aromatics which are substituted with OH,C(O)OH, and/or F; arenes that are substituted with OH, C(O)OH, and/or F;and acrylics which are substituted with OH, C(O)OH, and/or F.

Examples of preferred R₁ include:

In the present embodiment, R₂ is not limited to any specific carbonfunctional group, and is preferably selected from among linear orbranched alkyls, cylcoalkyls, aromatics, arenes, and acrylates.

The silsesquioxane polymers have a weight averaged molecular weight of400 to 500,000 atomic mass units, and more preferable from 1500 to10,000 atomic mass units. The R₁ and R₂ proportions and structures areselected to provide a material suitable for photolithographic processes,while also maintaining pattern fidelity after post patterning cure.

A second polymer component of the blend material includes but is notlimited to a family of organosilicates known as silsesquioxanes, havingthe structural formula:

wherein R₃ is preferable selected from alkyls, cycloalkyls, aryl, or acombination thereof, and are commercially available from Dow Corning,Inc., Shin-Etsu, Inc., or JSR Corporation, for example. Thesilsesquioxane is preferably poly(methylsilsesquioxane), and n is aninteger about 10 to about 1,000 or more (including copolymers). Thesilsesquioxane polymers possess silanol end groups, but may also includehalosilanes, acetoxysilanes, silylamines, and alkoxysilanes. In apreferred embodiment of the present invention, silsesquioxane polymers,LKD-2021 or LKD-2056 (from JSR Corporation) which contain silanol endgroups are employed.

The composition of the silsesquioxane polymers in the blend formulationis 1 to 99% of the total polymer composition. In the preferredembodiment of the invention, the composition of the acid sensitivepolymer is 20 to 80% of the total polymer composition, and even morepreferred, 30 to 60%.

A third component of the imageable first inter-level dielectric layer 22of the present embodiment is a pore-generating compound, called aporogen. The porogen provides nanoscopic pores in the composition ofmatter of the present invention which further reduces the dielectricconstant of the first imageable inter-level dielectric layer 22.

The porogen that can be used includes miscible or phase separated (i.e.,non-miscible) polymers that are capable of decomposing under heat orradiation. Alternatively, the porogen may be extracted withsupercritical fluid techniques. Examples of porogens that may beemployed include, but are not limited to, homopolymers, copolymers,organic nanoscopic polymers, thermoplatic polymers, star-shapedpolymers, dendrimers or crosslinked polymers that remain substantiallydormant during the patterning process. After patterning, the poregenerating polymers are decomposed or extracted to enhance thedielectric properties of the material of the present invention withoutseverely degrading the pattern fidelity. The decomposition of theporogen may be by heat-induced or radiation-induced, or other methodsmay alternatively be used.

When a porogen is employed, the porogen is present in the composition inan amount of from 1 to 9 weight percent of the functionalized polymer.More preferably, the porogen is present in an amount of from 5 to 50weight percent of the functionalized polymer.

A fourth component of the imageable first inter-level dielectric layer22 is a photosensitive acid generator (PAG) that is compatible with theother components. Non-limiting examples of preferred photosensitive acidgenerators include-(trifluoro-methylsulfonyloxy)-bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide(MDT), onium salts, aromatic diazonium salts, sulfonium salts,diaryliodonium salts, and sulfonic acid esters of N-hydroxyamides or-imides, as disclosed in U.S. Pat. No. 4,371,605. The content of the'605 patent is incorporated herein by reference. A weaker acid generatedfrom a photosensitive acid generator such as N-hydroxy-naphthalimide(DDSN) may be used. Combinations of photosensitive acid generators maybe used.

Condensation in the presence of an acid generated by a photoacidgenerator under exposure to radiation is not limited to silanols, butmay also include halosilanes, acetoxysilanes, silylamines, andalkoxysilanes. Organic crosslinking agents, such asmethylphenyltetramethoxymethyl glycouril (methylphenyl powderlink), mayalso be included in the formulation. Although photoacid generators arepreferred for crosslinking, photobase generators can also be used forcrosslinking silanol polymers.

The material from which is formed the first imageable inter-leveldielectric layer 22 of the instant embodiment may also include a castingsolvent to dissolve the other components. Non-limiting examples ofsuitable casting solvent include, but are not limited to,ethoxyethylpropionate (EEP), a combination of EEP and γ-butyrolactone,propylene-glycol monomethylether alcohol and acetate, propyleneglycolmonopropyl alcohol and acetate, and ethyl lactate. Combinations of thesesolvents may also be used.

In optimizing a photolithography process, an organic base may be addedto the composition for forming the first imageable inter-leveldielectric layer 22. The base employed may be any suitable base known inthe resist art. Examples of bases include tetraalkylammonium hydroxides,cetyltrimethylammonium hydroxide, and 1,8-diaminonaphthalene. Thecompositions used in this disclosure are not limited to any specificselection of base.

The term “acid-sensitive” is used throughout the application to denoteimageable functional groups which undergo a chemical reaction in thepresence of an acid generated by a photoacid generator under exposure toactinic imaging radiation. The acid-sensitive imageable functionalgroups employed in the present invention may include acid-sensitivepositive-tone functional groups or acid-sensitive negative-tonefunctional groups. The negative-tone acid-sensitive functional groupsare functional groups for causing a crosslinking reaction which causesthe exposed areas to be insoluble in a developer to form a negative-tonerelief image after development. The positive-tone acid-sensitivefunctional groups are acid-sensitive protecting groups which cause theexposed region to be soluble in a developer to form positive-tone reliefimages after development.

The aforementioned first imageable inter-level dielectric layer 22 usesmaterials that act as a photoresist for patterning; which may bepositive-tone or negative-tone, and sensitive to G-line, I-line, DUV(248 nm, 193 nm, 157 nm, 126 nm, and EUV (13.4 nm) radiation sources.

FIG. 4 shows the results of imaging and developing the first imageableinter-level dielectric layer 22 to provide a patterned first inter-leveldielectric layer 22′ and developing the developable bottomanti-reflective coating 20 to form a patterned bottom anti-reflectivecoating 20′, which in an aggregate provide a damascene aperture Al. Suchimaging and developing may be effected using methods and materials thatare otherwise generally conventional in the microelectronic fabricationart, in particular as is appropriate to a particular tone of the firstimageable inter-leevel dielectric layer 22.

FIG. 5 shows a second imageable inter-level dielectric layer 24 locatedand formed upon the microelectronic structure of FIG. 4. The secondimageable inter-level dielectric layer 24 may comprise an imageableinter-level dielectric material analogous, equivalent or identical tothe imageable inter-level dielectric material from which may becomprised the first imageable inter-level dielectric layer 22 that isillustrated in FIG. 3. Within the context of the instant embodiment, toprovide the microelectronic structure of FIG. 5, the first patternedinter-level dielectric layer 22′ will typically comprise a negative toneimageable inter-level dielectric material while the second imageableinter-level dielectric layer 24 may comprise either a positive tone or anegative tone imageable inter-level dielectric material. Typically thesecond imageable inter-level dielectric layer 24 has a thickness from 50to 2000 nanometers.

FIG. 6 shows the results of imaging and developing the second imageableinter-level dielectric layer 24 to form a second patterned inter-leveldielectric layer 24′ which in conjunction with the first patternedinter-level layer 22′ and the patterned bottom anti-reflective coatinglayer 20′ provide a dual damascene aperture A2 from the damasceneaperture A1. Imaging and developing of the second imageable inter-leveldielectric layer 24 to form the second patterned inter-level dielectriclayer 24′ may be effected using photolithographic exposure anddevelopment methods and materials that are otherwise generallyconventional in the microelectronic fabrication art, and otherwiseanalogous, equivalent or identical to the methods and materials that areused for forming the patterned first inter-level dielectric layer 22′that is illustrated in FIG. 4 from the first imageable inter-leveldielectric layer 22 that is illustrated in FIG. 3.

FIG. 7 shows a second barrier layer 26 located and formed within thedual damascene aperture A2 that is illustrated in FIG. 6. FIG. 7 alsoshows a second conductor layer 28 located and formed upon the secondbarrier layer 26.

Within this particular embodiment, the second barrier layer 26 and thesecond conductor layer 28 may comprise materials, have dimensions and beformed using methods that are otherwise generally conventional in themicroelectronic fabrication art. Such methods, materials and dimensionsmay also correspond with the methods, materials and dimensions that areused when fabricating the first barrier layer 14 and the first conductorlayer 16.

FIG. 7 shows a schematic cross-sectional diagram of a microelectronicstructure in accordance with a particular embodiment of the invention.

The particular microelectronic structure in accordance with theparticular embodiment includes the substrate 10 that further includesthereover the first conductor layer 16 embedded within the basedielectric layer 12. The first capping layer 18 is located and formedaligned upon the first conductor layer 16. The microelectronic structurealso includes a patterned bottom anti-reflective coating layer 20′, afirst patterned inter-level dielectric layer 22′ and a second patternedinter-level dielectric layer 24′ that in an aggregate comprise anddefine a dual damascene aperture A2 into which is located and formed asecond barrier layer 26 and then a second conductor layer 28.

Within the microelectronic structure whose schematic cross-sectionaldiagram is illustrated in FIG. 7, the patterned bottom anti-reflectivecoating layer 20′ includes an element selected from the group consistingof C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. In addition, each of thepatterned first inter-level dielectric layer 20′ and the patternedsecond inter-level dielectric layer 22′ comprises at least one organicfunctionalized silicon containing dielectric material. Within thecontext of the disclosure above, the microelectronic structure whoseschematic cross-sectional diagram is illustrated in FIG. 7 may befabricated absent dry plasma etch processing.

The preferred embodiment of the invention is illustrative of theinvention rather than limiting of the invention. Revisions andmodifications may be made to methods, materials, structures anddimensions of a microelectronic structure in accordance with thepreferred embodiment, while still providing a microelectronic structurein accordance with the invention, further in accordance with theaccompanying claims.

1. A microelectronic structure comprising: a first conductor layerlocated within a base dielectric layer located over a substrate; apatterned bottom antireflective coating layer located upon the basedielectric layer; and at least one patterned inter-level dielectriclayer located upon the patterned bottom anti-reflective coating layer,wherein: the patterned bottom anti-reflective coating layer and the atleast one patterned inter-level dielectric layer define an aperturelocated over the first conductor layer; the patterned bottomanti-reflective coating layer includes an element selected from thegroup consisting of C, Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; and theat least one patterned inter-level dielectric layer comprises a curedorganic functionalized silicon containing dielectric material.
 2. Themicroelectronic structure of claim 1 wherein the substrate comprises adielectric substrate.
 3. The microelectronic structure of claim 1wherein the substrate comprises a semiconductor substrate.
 4. Themicroelectronic structure of claim 1 wherein the first conductor layercomprises a copper containing conductor material.
 5. The microelectronicstructure of claim 1 wherein the aperture comprises a damasceneaperture.
 6. The microelectronic structure of claim 1 wherein theaperture comprises a dual damascene aperture.
 7. The microelectronicstructure of claim 1 further comprising a second conductor layer locatedwithin the aperture.
 8. The microelectronic structure of claim 1 whereinthe patterned bottom anti-reflective coating layer includes an elementselected from the group consisting of Ge, B, Sn, Fe, Ta, Ti, Ni, Hf andLa, without Si and without C.
 9. The microelectronic structure of claim1 wherein said base dielectric layer has a dielectric constant greaterthan 4.3 to 20, measured in vacuum, and is selected from the groupconsisting of silicon oxide dielectric materials, silicon nitridedielectric materials and silicon oxynitride dielectric materials. 10.The microelectronic structure of claim 1 wherein said base dielectriclayer has a dielectric constant from 1.0 to less than 4.3, measured invacuum, and is selected from the group consisting of spin-on-glassdielectric materials, spin-on-polymer dielectric materials, micro-porousdielectric materials, nano-porous dielectric materials, carbon dopedsilicate glass dielectric materials and fluorine doped silicate glassdielectric materials.
 11. A microelectronic structure comprising: afirst conductor layer located within a base dielectric layer locatedover a substrate; a first conductor capping layer located aligned uponthe first conductor layer; a patterned bottom anti-reflective coatinglayer located upon the base dielectric layer; and at least one patternedinter-level dielectric layer located upon the patterned bottomanti-reflective coating layer, wherein: the patterned bottomanti-reflective coating layer and the at least one patterned inter-leveldielectric layer define an aperture that exposes the first conductorcapping layer; the developed bottom anti-reflective coating layerincludes an element selected from the group consisting of C, Si, Ge, B,Sn, Fe, Ta, Ti, Ni, Hf and La; and the at least one patternedinter-level dielectric layer comprises an organic functionalized siliconcontaining dielectric material.
 12. The microelectronic structure ofclaim 11 wherein the first conductor layer is coplanar with the basedielectric layer.
 13. The microelectronic structure of claim 11 whereinthe first conductor capping layer is coplanar with the base dielectriclayer.
 14. The microelectronic structure of claim 11 wherein thepatterned bottom anti-reflective coating layer includes an elementselected from the group consisting of Ge, B, Sn, Fe, Ta, Ti, Ni, Hf andLa.
 15. The microelectronic structure of claim 11 wherein said basedielectric layer has a dielectric constant greater than 4.3 to 20,measured in vacuum, and is selected from the group consisting of siliconoxide dielectric materials, silicon nitride dielectric materials andsilicon oxynitride dielectric materials.
 16. The microelectronicstructure of claim 11 wherein said base dielectric layer has adielectric constant from 1.0 to less than 4.3, measured in vacuum, andis selected from the group consisting of spin-on-glass dielectricmaterials, spin-on-polymer dielectric materials, micro-porous dielectricmaterials, nano-porous dielectric materials, carbon doped silicate glassdielectric materials and fluorine doped silicate glass dielectricmaterials.
 17. The microelectronic structure of claim 11 said whereinorganic functionalized silicon containing dielectric material includessilicon-containing substituents.
 18. The microelectronic structure ofclaim 17 wherein said silicon-containing substituents are selected fromthe group consisting of are trimethylsilyl alkyl acrylate,trimethylsilyl alkyl methacrylate, trimethylsilyl alkyl itaconate,tris(trimethylsilyl)silyl alkyl acrylate tris(trimethylsilyl)silyl alkylmethacrylate, tris(trimethylsilyl)silyl alkyl itaconate,tris(trimethylsilyloxy)silyl alkyl acrylate,tris(trimethylsilyloxy)silyl alkyl methacrylate,tris(trimethylsilyloxy)silyl alkyl itaconate, alkylsilyl styrene,trimethylsilylmethyl(dimethoxy)silyloxy alkyl acrylate,trimethylsilylmethyl(dimethoxy)silyloxy alkyl methacrylate,trimethylsilylmethyl(dimethoxy)silyloxy alkyl itaconate, trimethylsilylalkyl norbornene-5-carboxylate alkyl, tris(trimethylsilyl)silyl alkylnorbornene-5-carboxylate and tris(trimethylsilyloxy)silyl alkylnorbornene-5-carboxylate, wherein alkyl is a C₁₋₅ moiety.